Dynamic semiconductor memory device

ABSTRACT

A dynamic semiconductor memory device incorporating memory cells of a one-transistor and one-capacitor type is provided with increased charge storage and thus improved read operation. In this device, each of the memory cells is connected to one word line, to one bit line and to one power supply line. The potential of the power supply line is toggled low then high so as to store more charges in the capacitor of a memory cell.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor memory device and, more particularly, to an MIS (Metal-Insulator-Semiconductor) dynamic memory device of a one-transistor and one-capacitor type.

In general, an MOS (broadly, MIS) dynamic memory device of a one-transistor and one-capacitor type incorporates memory cells, each comprising a transistor and a capacitor. In this case, the transistor serves as a switching gate for charging or discharging the capacitor. In addition, the presence of charges in the capacitor corresponds to the data "0" or "1". For example, the state in which the capacitor is discharged corresponds to the data "0", while the state in which the capacitor is charged corresponds to the data "1".

The above-mentioned transistor has a gate connected to a word line, a drain connected to a bit line and a source. The source is connected to one electrode of a capacitor. This capacitor has another electrode connected to a power supply, which is usually the ground or another power supply V_(cc). In the stand-by state, the bit line is precharged by the power supply V_(cc).

Therefore, if the data "0" is stored in the memory cell, a charge Q₁ stored in the capacitor thereof is

    Q.sub.1 =0.

Contrary to the above, if the data "1" is stored in the memory cell, a charge Q₂ stored in the capacitor thereof is

    Q.sub.2 =C(V.sub.cc -V.sub.th)

where C is the capacitance of the capacitor;

V_(cc) is also a voltage of the power supply V_(cc) ; and

V_(th) is a threshold voltage of the transistor. Therefore, the difference ΔQ between the charges Q₁ and Q₂ is

    ΔQ=C(V.sub.cc -V.sub.th)

However, in the above-mentioned memory cell in which the other electrode of the capacitor is connected to the power supply V_(cc) or the ground, in other words, the potential of the other electrode is definite, the difference ΔQ is relatively small. This leads to an unstable read operation, since the operation of a sense amplifier for amplifying the difference in potential between the bit lines is dependent upon the difference ΔQ.

SUMMARY OF THE INVENTION

It is a principal object of the present invention to provide a semiconductor memory device with a stable read operation.

According to the present invention, there is provided a semiconductor memory device comprising: first and second power supplies, the potential of the second power supply being lower than that of the first power supply; a plurality of word lines; a plurality of power supply lines; a plurality of pairs of bit lines; a plurality of sense amplifiers, arranged between a respective pair of the pairs of bit lines; and a plurality of memory cells, each comprising a transistor and a capacitor. The transistor has a gate connected to one of the word lines and a drain connected to one of the bit lines; the capacitor has an electrode connected to a source of the transistor and another electrode connected to one of the power supply lines. The semiconductor memory device further comprises a plurality of means, connected to one of the power supply lines, for supplying a clock signal thereto after the rising of the potential of one of the word lines, wherein the potential of the clock signal falls and after that, rises. In the present invention, the difference between the charges Q₁ and Q₂ corresponding to the data "0" and "1" is increased due to the bootstrap effect, without changing the structure of the memory cells.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more clearly understood from the following description contrasting the present invention with the conventional device and with reference to the accompanying drawings, wherein:

FIG. 1A is a cross-sectional view illustrating a memory cell of a one-transistor and one-capacitor type;

FIG. 1B is an equivalent circuit diagram of the memory cell of FIG. 1A;

FIGS. 2A and 2B are a block diagram of a conventional semiconductor memory device;

FIG. 3 is a circuit diagram of a part of the device of FIG. 2;

FIGS. 4A, 4B and 4C are timing diagrams of the signals appearing in the circuit of FIG. 3;

FIGS. 5, 5A and 5B are block diagram of an embodiment of the semiconductor memory device according to the present invention;

FIG. 6 is a circuit diagram of a part of the device of FIG. 5;

FIGS. 7A, 7B and 7C are timing diagrams of the signals appearing in the circuit of FIG. 6;

FIGS. 8, 8A and 8B are a block diagram illustrating another embodiment of the semiconductor memory device according to the present invention;

FIG. 9 is a circuit diagram of a part of the device of FIG. 8; and

FIGS. 10A, 10B and 10C are timing diagrams of the signals appearing in the circuit of FIG. 9.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1A, which illustrates a one-transistor and one-capacitor type memory cell, the memory cell is manufactured by using a so-called double-layer polycrystalline silicon technology. In FIG. 1A, 1 is a semiconductor substrate which is, for example, p⁻ -type monocrystalline silicon; 2 is a field layer which is relatively thick and made of, for example, silicon dioxide; 3 and 5 are insulating layers which are relatively thin and made of, for example, silicon dioxide; 4 and 6 first and second conductive layers, respectively, and made of, for example, polycrystalline silicon; and 7 is an n⁺ -type impurity doped region. In this case, an MOS transistor Q_(m) comprises a source formed by an inversion layer within the substrate 1 under the insulating layer 3, a drain formed by the impurity doped region 7 and a gate formed by the second conductive layer 6, while a capacitor C_(m) comprises one electrode formed by the substrate and the other electrode formed by the first conductive layer 4 with the insulating layer 3 therebetween. Of course, various kinds of memory cells of a one-transistor and one-capacitor type have been developed; however, the memory cell as illustrated in FIG. 1A is a representative one which has an advantage in that the integrated density thereof is high.

FIG. 1B is an equivalent circuit diagram of the memory cell of FIG. 1A. In FIG. 1B, in the transistor Q_(m), a drain D and a gate G are connected to a bit line BL_(j) and a word line WL_(i), respectively, and in addition, a source S is connected to an electrode P₁ of the capacitor C_(m) which, in turn, has a electrode P₂ connected to a power supply line PL. In general, the power supply line PL is grounded.

The transistor Q_(m) is used for charging or discharging the capacitor C_(m). For example, when the potential of the word line WL_(i) is high (in this case, the transistor Q_(m) is of an n-channel type), the bit line BL_(j) is electrically connected to the electrode P₁ of the capacitor C_(m) so that a charge is transferred from the bit line BL_(j) to the electrode P₁ or vice versa in response to the potential of the bit line BL_(j). In this case, the absence or presence of a charge in the electrode P₁ of the capacitor C_(m) corresponds to the data "0" or "1" respectively.

FIG. 2 is a block diagram illustrating a conventional semiconductor memory device incorporating a plurality of the above-mentioned memory cells of a one-transistor and one-capacitor type. In FIG. 2, for example, 16,384 memory cells C₀₀, C₀₁, . . . , C₀,127 ; C₁₀, C₁₁, . . . , C₁,127 ; . . . , C₁₂₇,127 are arranged in 128 rows and 128 columns to form matrixes at intersections of word lines WL₀, . . . , WL₆₃, WL₆₄, . . . , WL₁₂₇ and bit lines BL₀, BL₀, BL₁, BL₁, . . . , BL₁₂₇, BL₁₂₇. In this case, each sense amplifier, SA₀, SA₁, . . . , SA₁₂₇, is located between each pair of the bit lines, such as BL₀ and BL₀, with each bit line being connected to a respective side of the sense amplifier.

In addition, dummy memory cells DC₀₀, DC₀₁, . . . , DC₀,127 are connected to the bit lines BL₀, BL₁, . . . , BL₁₂₇, respectively, while dummy memory cells DC₁₀, DC₁₁, . . . , DC₁,127 (FIG. 2B) are connected to the bit lines BL₀, BL₁, . . . , BL₁₂₇, respectively. Further, transistors Q_(a0), Q_(a1), . . . , Q_(a),127 are connected to the bit lines BL₀, BL₁, . . . , BL₁₂₇, respectively, in order to precharge these bit lines, while, transistors Q_(b0), Q_(b1), . . . , Q_(b),127 (FIG. 2B) are connected to the bit lines BL₀, BL₁, . . . , BL₁₂₇, respectively, in order to precharge these bit lines.

In order to select one of the word lines WL₀, . . . , WL₆₃, WL₆₄, . . . , WL₁₂₇, word decoders WD₀, . . . , WD₆₃, WD₆₄, . . . , WD₁₂₇ each comprising an NOR gate, are connected to the word lines through gates G₀, . . . , G₆₃, G₆₄, . . . , G₁₂₇ which are controlled by a clock signal φ_(WL). In addition, in order to select one of dummy word lines DWL₀ and DWL₁, dummy word decoders DWD₀ and DWD₁ each comprising an NOR gate are connected to the dummy word lines through gates G₋₁ and G₁₂₈ which are also controlled by the clock signal φ_(WL). In this case, each of the word decoders WD₀, . . . , WD₆₃, WD₆₄, . . . , WD₁₂₇ receives a combination of seven signals A₀, A₀, . . . , A₆, A₆, selected from fourteen address signals, while each of the dummy word decoders DWD₀ and DWD₁ receives a signal, for example, the address signal A₆ and A₆, respectively.

The operation of the device of FIG. 2 will be explained by using FIG. 3 and FIGS. 4A, 4B and 4C. FIG. 3 is a circuit diagram of a part of the device of FIG. 2, for explaining the read operation of the memory cell C₀₀ and FIGS. 4A, 4B and 4C are timing diagrams of the signals appearing in the circuit of FIG. 3. In more detail, FIGS. 4B and 4C are used for explaining the read operation for reading the data "0" and "1", respectively. Note that the capacitance of a capacitor C_(d) of the dummy memory cell DC₁ is about one-half of that of a capacitor C_(m) of the memory cell C₀₀.

In FIG. 3, the sense amplifier SA₀ comprises two cross-coupled transistors Q_(c) and Q_(d) which constitute a flip-flop, and two transistors Q_(e) and Q_(f) for pulling up the bit lines BL₀ and BL₀. In addition, the bit lines BL₀ and BL₀ are connected to data bus lines DB and DB, respectively, by transistors Q_(g) and Q_(h) controlled by a column selection signal CL₀ which are, however, not shown in FIG. 2. In addition, the dummy cell DC₁ comprises a transistor Q_(d1) and a capacitor C_(d) which are similar to the transistor Q_(m) and the capacitor C_(m), respectively, of the memory cell C₀₀ and in addition, a transistor Q_(d2) for discharging the capacitor C_(d) in the stand-by state.

In the stand-by state, the transistors Q_(a0) and Q_(b0) are turned on by the potential of the reset signal RST being high, so that the bit lines BL₀ and BL₀ are precharged to the power supply voltage V_(cc) and simultaneously, a transistor Q_(d2) of the dummy memory cell DC₁ is also turned on, so that the capacitor C_(d) is discharged; that is, the potential at a node N₂ is the power supply voltage V_(ss) (ground). After that, the potential of the reset signal RST returns to the voltage V_(ss) so that the bit lines BL₀ and BL₀ are floating.

In order to read the data stored in the cell C₀₀, the word decoder WD₀ (FIG. 2) is triggered and as illustrated in FIG. 4A, the potential of the clock signal φ_(WL) rises, so that the potential V_(WL) of the word line WL₀ rises at a time t₁, and accordingly the transistor Q_(m) conducts. As a result, if the data stored in the cell C₀₀ is "0", a current flows from the bit line BL₀ into a node N₁ of the cell C₀₀, so that, as illustrated in FIG. 4B, the potential V_(BL) of the bit line BL falls from V_(cc) to V_(cc) -ΔV_(BL) and in turn, the potential V_(N1) at the node N₁ rises from V_(ss) to V_(cc) -V_(th), where V_(th) is a threshold voltage of the transistor Q_(m). In this case, the voltage-drop ΔV_(BL) is ##EQU1## where C_(B) and C are capacitances of the bit line BL and the capacitor C_(m), respectively. On the other hand, simultaneously, the dummy word decoder DWD₁ (FIG. 2) is triggered so that the potential V_(DW1), as illustrated in FIG. 4A, of the dummy word line DWL₁ rises and accordingly, a transistor Q_(d1) conducts. As a result, a current flows from the bit line BL₀ into a node N₂ of the dummy memory cell DC₁, so that, as illustrated in FIG. 4B, the potential V_(BL) of the bit line BL₀ falls from V_(cc) to V_(cc) -ΔV_(BL) and in turn, the potential V_(N2) at the node N₂ rises from V_(ss) to V_(cc) -V_(th). In this case, the voltage-drop ΔV_(BL) is selected so as to satisfy ΔV_(BL) =1/2ΔV_(BL).

Contrary to the above, if the data stored in the cell C₀₀ is "1", no current flows from the bit line BL₀ into the node N₁ of the cell C₀₀, so that the potential V_(BL) of the bit line BL remains at the same level V_(cc) and the potential V_(N1) at the node N₁ also remains at the same level V_(cc) -V_(th). On the other hand, in the dummy memory cell DC₁, as in the case where the data "0" is stored, the potential V_(BL) of the bit line BL₀ falls from V_(cc) to V_(cc) -ΔV_(BL) and in turn, the potential V_(N2) at the node N₂ rises from V_(ss) to V_(cc) -V_(th), as illustrated in FIG. 4C.

In any case, the difference 1/2ΔV_(BL) in potential between the bit lines BL₀ and BL₀ is generated. Therefore, at a time t₂, the potential V_(LE) of a latch enable signal LE rises so as to trigger the sense amplifier SA₀. As a result, one of the potentials V_(BL) and V_(BL) reaches V_(cc) and the other reaches V_(ss).

Note that, in FIG. 4B, at a time t₃, the potential V_(BL) of the bit line BL₀ rises from V_(cc) -ΔV_(BL) to V_(cc) due to the active pull-up effect, since the potential of a signal φ₁ rises so that the transistors Q_(e) and Q_(f) become conductive.

Next, by causing the potential of a column selection signal CL₀ to be high, the potentials of the bit lines BL₀ and BL₀ are transmitted into an input/output amplifier (not shown) through the data bus lines DB and DB. After the read operation is completed, the potential V_(WL) of the word line WL₀ becomes V_(ss) so that the memory device is in the stand-by state. At this time, the data "0" or "1" is stored in the memory cell C₀₀.

In the case of the data "0" being stored in the memory cell C₀₀, the charge Q₁ =0 is stored in the capacitor C_(m), while, in the case of the data "1"being stored in the memory cell C₀₀, the charge Q₂ =C(V_(cc) -V_(th)) is stored in the capacitor C_(m). Therefore, the difference ΔQ in charges between the data "0" and "1" is ΔQ=C(V_(cc) -V_(th)). In the present invention, the difference ΔQ is increased so as to increase the difference in potential between the bit lines BL₀ and BL₀ prior to the operation of the sense amplifier SA₀, this increases the stability of the sense amplifier SA₀ operation.

FIG. 5 is a block diagram illustrating an embodiment of the semiconductor memory device according to the present invention. In FIG. 5, the elements which are the same as those of FIG. 2 are denoted by the same references. In FIG. 5, the memory cells C₀₀, C₀₁, . . . , C₀,127 ; C₁₀, C₁₁, . . . , C₁,127 ; . . . , C₁₂₇,127 are connected to power supply lines WL₀, . . . , WL₆₃, WL₆₄, . . . , WL₁₂₇, not to the power supply V_(ss) (ground). In this case, the potentials of the power supply lines WL₀, . . . , WL₆₃, WL₆₄, . . . , WL₁₂₇ are changeable. However, the dummy memory cells DC₀₀, DC₀₁, . . . , DC₀,127 and DC₁₀, DC₁₁, . . . , DC₁,127 of FIG. 2 are not provided. Further, the potential for precharging the bit lines BL₀ and BL₀ is V_(cc) -V_(th) -α. Here, α is a voltage necessary for maintaining the conduction of the transistor Q_(m) when the potential V_(WL) of the word line WL₀ is V_(cc).

In the present invention, the charges stored in the capacitors C of the memory cells are increased by causing the potentials of the power supply lines WL₀, . . . , WL₆₃, WL₆₄, . . . , WL₁₂₇ to be low and after that, to be high. The changes of the potentials of the power supply lines WL₀, . . . , WL₆₃, WL₆₄, . . . , WL₁₂₇ can be effected by a clock signal φ_(WL) through gates G₀ ', . . . , G₆₃ ', G₆₄ ', . . . , G₁₂₇ '.

The operation of the device of FIG. 5 will be explained by using FIG. 6 and FIGS. 7A, 7B and 7C. Here, FIG. 6 is a circuit diagram of a part of the device of FIG. 5 and FIGS. 7A, 7B and 7C are timing diagrams of the signals appearing in the circuit of FIG. 5. In more detail, FIGS. 7B and 7C are used for explaining the read operation for reading the data "0" and "1", respectively.

In the stand-by state, the transistors Q_(a0) and Q_(b0) (FIG. 5) are turned on by causing the potential of the reset signal RST to be high, during this time the bit lines BL₀ and BL₀ are precharged to V_(cc) -V_(th) -α. After the charging, the potential of the signal RST returns to the voltage V_(ss) (ground) placing the bit lines BL₀ and BL₀ in a floating state.

In order to read the data stored in the cell C₀₀, the word decoder WD₀ (FIG. 5) is triggered and, as illustrated in FIG. 7A the potential of the clock signal φ_(WL) rises, so that the potential V_(WL) of the word line WL₀ rises at a time t₁. As a result, the transistor Q_(m) conducts and accordingly, if the data stored in the cell C₀₀ is "0," a current flows from the bit line BL₀ into the node N₁ of the cell C₀₀. Therefore, as illustrated in FIG. 7B, the potential V_(BL) of the bit line BL falls from the precharged potential V_(cc) -V_(th) -α to V_(cc) -V_(th) -α-ΔV_(BL) and in turn, the potential V_(N1) at the node N₁ rises from V_(ss) to V_(cc) -V_(th) -αΔV_(BL). In this case, the voltage-drop ΔV_(BL) is ##EQU2## On the other hand, the potential V_(BL) of the bit line BL₀ remains at the same level, since there is no dummy memory cell connected to the bit line BL₀.

At a time t₂ when the potential V_(LE) of the latch enable signal LE rises as illustrated in FIG. 7A, the sense amplifier SA₀ is triggered so as to amplify the potential difference ΔV_(BL), as illustrated in FIG. 7B. After that, the potential of the signal φ₁ rises as illustrated in FIG. 7A, and the potential V_(BL) of the bit line BL is pulled up to V_(cc) via transistor Q_(f). Thus, the read operation for the data "1" is completed.

Next, as illustrated in FIG. 7A, the potential of the signal φ_(WL) falls from V_(cc) to V_(ss) and after that, again, it rises from V_(ss) to V_(cc). Accordingly, at a time t₃, the potential V_(WL) of the power supply line WL₀ falls from V_(cc) to V_(ss) and, at a time t₄, it rises from V_(ss) to V_(cc). During the falling of the potential V_(WL), the potential V_(N1) falls due to the capacitive coupling of the line WL₀ and the node N₁ ; however, the potential V_(N1) immediately returns to V_(ss) due to transistor Q_(m) being ON, as illustrated in FIG. 7B. In this case, a small quantity of charges is stored in the capacitor C_(m). After that, during the rising of the potential V_(WL), the potential V_(N1) rises also due to capacitive coupling; however, also in this case, the potential V_(N1) returns to V_(ss), so that the charges stored in the capacitor C_(m) flow out. Thus, the refresh operation for the data "0" is completed.

It should be noted that, in the above-mentioned operation, the transistor Q_(m) is always conductive, since the difference in potential between the gate and the source (or drain) is larger than the threshold voltage V_(th) of the transistor Q_(m).

Contrary to the above, if the data stored in the cell C₀₀ is "1," that is, the potential V_(N1) at the node N₁ is higher than V_(cc) -V_(th) -α, a current flows from the node N₁ to the bit line BL₀ when the potential V_(WL) of the word line WL₀ is V_(cc). As a result, the potential V_(BL) of the bit line BL₀ rises, while, the potential V_(BL) of the bit line BL remains at the level V_(cc) -V_(th) -α. In this case, the difference in potential between the bit lines BL₀ and BL₀ is defined as ΔV_(BL), as illustrated in FIG. 7C. At the time t₂, the difference ΔBL is amplified so that the potential V_(BL) of the bit line BL₀ reaches V_(cc) and the potential V_(BL) of the bit line BL₀ reaches V_(ss). In this case, the potential V_(N1) at the node N₁ is V_(cc) -V_(th).

As illustrated in FIG. 7A, at the time t₃ when the potential V_(WL) of the power supply line WL₀ is changed from V_(cc) to V_(ss), the potential V_(N1) at the node N₁ falls due to the capacitive coupling, as illustrated in FIG. 7C, so that a current flows from the bit line BL₀ into the node N₁. As a result, a quantity of charges is stored in the capacitor C_(m). Next, at the time t₄ when the potential V_(WL) is changed from V_(ss) to V_(cc), the potential V_(N1) at the node N₁ rises so that the charges stored in the capacitor C_(m) tend to flow out; however, in this state, the charges never flow out. This is because, at this time, the potential V_(WL) applied to the gate of the transistor Q_(m) and the potential V_(BL) applied to the drain of transistor Q_(m) are both V_(cc), so that the transistor Q_(m) is non-conductive. Therefore, when the potential V_(WL) of the power supply line WL₀ is changed from V_(ss) to V_(cc), a value V_(cc) is added to the potential V_(N1) at the node N₁ so that this potential V_(N1) becomes 2V_(cc) -V_(th). This is a so-called bootstrap effect. Thus, after the read operation and the refresh operation for the data "1" are completed, the charge (2V_(cc) -V_(th))×C is stored in the capacitor C_(m).

Therefore, prior to the read operation for the data "1", the potential V_(N1) at the node N₁ is 2V_(cc) -V_(th), as illustrated in FIG. 7C. In this state, again at the time t₁ when the potential V_(WL) of the word line WL₀ is changed from V_(ss) to V_(cc), a current flows from the node N₁ into the bit line BL₀, so that the potential V_(N1) at the node N₁ is decreased and in turn, the potential V_(BL) of the bit line BL₀ is increased. In this case, the voltage-increase ΔV_(BL) of the potential V_(BL) is ##EQU3## On the other hand, the potential V_(BL) of the bit line BL₀ remains at the same level V_(cc) -V_(th) -α, since there is no dummy cell.

Thus, in the circuit of FIG. 6, the differences in potential between the bit lines BL₀ and BL₀, prior to the operation of the sense amplifier SA₀, are ##EQU4## for the data "0" and "1", respectively. As compared with the conventional circuit of FIG. 3 in which such a difference is ##EQU5## the increase of the charge stored in the capacitor C_(m) contributes to the increase of the difference in potential between the bit lines BL₀ and BL₀, which means that the stored charges in the capacitor C_(m) are helpful in the read operation.

In the above-mentioned embodiment, the difference in potential between the bit lines BL₀ and BL₀ for the data "0" is different from the difference for the data "1"; however, the two differences can be equal by providing an appropriate dummy memory cell.

FIG. 8 is a block diagram illustrating another embodiment of the semiconductor memory device according to the present invention. In FIG. 8, the elements which are the same as those of FIG. 5 are denoted by the same references. In FIG. 8, dummy memory cells DC₀₀, DC₀₁, . . . , DC₀,127; DC₁₀, DC₁₁, . . . , DC₁,127 are provided in addition to the memory cells in FIG. 5. In this case, the capacitance of a capacitor of the dummy memory cells is the same as that of the memory cells.

The operation of the device of FIG. 8 will be explained by using FIG. 9 and FIGS. 10A, 10B and 10C. Here, FIG. 9 is a circuit diagram of a part of the device of FIG. 8 and FIGS. 10A, 10B and 10C are timing diagrams of the signals appearing in the circuit of FIG. 9. In more detail, FIGS. 7B and 7C are used for explaining the read operation for reading the data "0" and "1", respectively.

In the stand-by state, the bit lines BL₀ and BL₀ are precharged to V_(cc). In order to read the data "0", at the time t₁ when the potentials V_(WL) and V_(DW1) are changed from V_(ss) to V_(cc), the potentials V_(BL) and V_(BL) of the bit lines BL₀ and BL₀ are both decreased from V_(cc) to V_(cc) -ΔV_(BL) (=ΔV_(BL)), as illustrated in FIG. 10B. The voltage-drop ΔV_(BL) (=ΔV_(BL)) is, in this case, ##EQU6## After that, at the time t₂ when the potential V_(WL) of the power supply line WL₀ is changed from V_(cc) to V_(ss), a current flows from the bit line BL₀ to the node N₁ of the cell C₀₀, so that the potential V_(BL) of the bit line BL₀ is further decreased by ##EQU7## As a result, the difference in potential between the bit lines BL₀ and BL₀ is ##EQU8##

On the other hand, if the data stored in the cell C₀₀ is "1", at the time t₁, a current flows from the bit line BL₀ to the node N₂ so that the potential V_(N2) at the node N₂ rises from V_(ss) to V_(cc) -V_(th) and in turn, the potential V_(BL) of the bit line BL₀ falls, as illustrated in FIG. 10C. In this case, the voltage-drop ΔV_(BL) is ##EQU9## On the other hand, in the memory cell C₀₀, the transistor Q_(m) remains non-conductive so that the potential V_(BL) of the bit line BL₀ remains at the level V_(cc). Next, at the time t₂, the falling of the potential V_(WL) of the power supply line WL₀ causes the potential V_(N1) at the node N₁, to also be decreased; however, even in this case, the transistor Q_(m) remains non-conductive so that the potential V_(BL) of the bit line BL remains at the level V_(cc). Therefore, the difference in potential between the bit lines BL₀ and BL₀ is ##EQU10##

After such a difference in potential between the bit lines BL₀ and BL₀ is generated, at the time t₃, the sense amplifier SA₀ is activated. As a result, as illustrated in FIGS. 10B and 10C, one of the potentials V_(BL) and V_(BL) reaches V_(ss) and the other reaches V_(cc). Further, at the time t₄ when the potential V_(WL) is changed from V_(ss) to V_(cc), the potential V_(N1) at the node N₁ returns to V_(ss) or 2V_(cc) -V_(th) in accordance with the data being "0" or "1", as illustrated in FIG. 10B, 10C respectively.

In the embodiment as illustrated in FIGS. 8, 9, 10A, 10B and 10C, the falling of the potential V_(WL) of the power supply line WL₀ follows the rising of the potential V_(WL) of the word line WL₀ ; however, the falling of the potential V_(WL) can occur simultaneously with the rising of the potential V_(WL), without problems. In addition, the two differences in potential between the bit lines BL₀ and BL₀ for the data being "0" and "1" can be the same by selecting the capacitance of the capacitor C_(d).

As explained hereinbefore, the present invention has an advantage, over the conventional device, in that the read operation is stable. This is because the charge stored in the memory cell can be about twice the usual charge, which increases the difference in potentials between a pair of bit lines prior to the operation of the sense amplifiers. 

I claim:
 1. A semiconductor memory device operatively connected to receive address signals and clock signals, said device comprising:first and second power supplies, the potential of said second power supply being lower than said first power supply potential; a plurality of word lines; a plurality of power supply lines; a plurality of pairs of bit lines; a plurality of sense amplifiers, respective of said sense amplifiers operatively connected between a corresponding pair of said pairs of bit lines; a plurality of memory cells, each comprising a transistor having a gate connected to a corresponding one of said word lines, a drain connected to a corresponding one of said bit lines, and a source, a capacitor having a predetermined capacitance and an electrode connected to the source of said transistor and another electrode connected to a corresponding one of said power supply lines; and clock means operatively connected to said power supply lines and to said word lines, for selectively supplying a clock signal to corresponding of said power supply lines in response to said address signals and after the potential of said corresponding word line rises and before the potential of said corresponding word line falls, the potential of said clock signal falls and after that, rises.
 2. A device as set forth in claim 1, wherein said clock signal falls from the potential of said first power supply to the potential of said second power supply and after that, rises from the potential of said second power supply to the potential of said first power supply.
 3. A device as set forth in claim 1 or 2, further comprising:two dummy word lines; and a plurality of dummy memory cells, respective of said dummy cells connected to a corresponding one of said bit lines, to a corresponding one of said two dummy word lines and to said second power supply.
 4. A device as set forth in claim 3, wherein each of said dummy memory cells comprises:a first dummy transistor having a drain connected to said corresponding one of said bit lines, a gate connected to said corresponding one of said two dummy word lines; a dummy capacitor having predetermined capacitance and a first electrode connected to a source of said first dummy transistor and a second electrode connected to receive said second power supply; and a second dummy transistor having a drain and a source connected to the first electrode and to the second electrode, respectively, and a gate for receiving a reset signal.
 5. A device as set forth in claim 4, wherein the capacitance of the dummy capacitor of said dummy memory cells is the same as that of the capacitor of said memory cells.
 6. The device as set forth in claim 3, wherein each of said sense amplifiers comprises means for latching data from said corresponding pair of said pairs of bit lines, and wherein said fall and rise of said clock signal occurs after said latching.
 7. A dynamic semiconductor memory device operatively connected to receive address signals and clock signals, a first power supply voltage, and a second power supply voltage lower than said first power supply voltage, comprising:a plurality of word lines, each having a potential; a plurality of power supply lines arranged parallel to said word lines; a plurality of bit line pairs, said bit line pairs and said word lines arranged in a matrix; a plurality of sense amplifiers, respective of said sense amplifiers operatively connected between a corresponding pair of said bit line pairs, and comprising means for latching data from said corresponding pair of said pairs of bit lines; a plurality of memory cells arranged at cross points of said matrix, each of said memory cells comprisinga transistor having a gate connected to a corresponding one of said word lines, a drain connected to a corresponding one of said bit lines, and a source, a capacitor having a predetermined capacitance, having a first electrode connected to the source of said transistor and having a second electrode connected to a corresponding one of said power supply lines; and clock means operatively connected to receive said clock signals and said address signals and operatively connected to said word lines and said power supply lines for providing a negative clock pulse to corresponding ones of said word lines and power supply lines responsive to corresponding ones of said address signals and of said clock signals, wherein said clock means comprises means for providing control signals responsive to said corresponding of said control signals and to said clock signals, for providing said negative clock pulse after the potential of at least one of said corresponding ones of said word lines rises and before said potential falls.
 8. A method of accessing a dynamic semiconductor memory device, which is operatively connected to receive address signals, a first power supply voltage, a second power supply voltage lower than the first power supply voltage, the device including power supply lines, word lines, bit line pairs, a memory cell array connected to the word lines, the power supply lines, and the bit line pairs, and sense amplifiers respectively connected to corresponding bit line pairs, each sense amplifier having an enable and disable state, said method comprising the sequential steps of:(a) precharging the bit line pairs to a predetermined voltage; (b) selecting one of the word lines, the sense amplifiers, the bit line pairs and the power supply lines; (c) applying the first power supply voltage to the selected word line; (d) enabling the selected sense amplifier; (e) applying the first power supply voltage to the selected bit line pair through the selected sense amplifier; (f) applying the second power supply voltage to the selected power supply line; (g) applying the first power supply voltage to the selected power supply line; and (h) applying the second power supply voltage to the selected word line. 